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cml semiconductor products baseband signal processor fx829 ? 1997 consumer microcircuits limited d/829/4 september 1997 1.0 features provisional issue rx audio processing multi-standard modem formats tx audio processing ets/mpt/paa standards compatible 1200/2400 baud modem low voltage operation dtmf encoder 24-pin small form package 1.1 brief description the fx829 is a low voltage cmos integrated circuit, designed to provide the baseband audio and system signal-processing functions required for pamr or pmr trunked radio applications. it operates in half-duplex mode under serial-bus control of the host c. the fx829 incorporates a dual-rate 1200/2400bps ffsk modem, with a software-flexible choice of synchronisation codewords, data run-length and crc checking to suit a wide range of applications. these features allow very flexible handling of non-prescribed data on traffic channels in addition to the network signalling sent on control channels. a 16 character dtmf encoder is available in the transmit mode. the two-point modulation output has software programmable level-adjustment. the audio processing stages include transmit and receive filtering, to the standards specified for 12.5khz and 25khz pamr/pmr channel operation, plus transmit deviation limiting and a programmable rx volume control. power saving is automatic when audio functions are deselected. the fx829 is designed for use in radios compatible with mpt1327, paa1382 and ets 300 086 trunking standards. its features and flexibility ensure that it is equally suitable for use with modified or proprietary standards.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 2 d/829/4 contents section page 1.1 brief description ................................ ................................ ......................... 1 1.2 block diagram ................................ ................................ ............................ 3 1.3 signal list ................................ ................................ ................................ ... 4 1.4 external components ................................ ................................ ................. 7 1.5 general description ................................ ................................ .................... 8 1.5.1 software description ................................ ................................ .. 9 1.5.2 ffsk checksum generation and checking ............................ 18 1.6 application notes ................................ ................................ ..................... 20 1.7 performance specification ................................ ................................ ....... 25 1.7.1 electrical performance ................................ .............................. 25 1.7.2 packaging ................................ ................................ .................. 32
baseband signal processor fx829 ? 1997 consumer microcircuits limited 3 d/829/4 1.2 block diagram figure 1 block diagram
baseband signal processor fx829 ? 1997 consumer microcircuits limited 4 d/829/4 1.3 signal list package d2/d5 signal description pin no. name type 1 xtaln o/p the inverted output of the on-chip oscillator. 2 xtal/clock i/p the input to the on-chip oscillator, for external xtal circuit or clock. 3 serial clock i/p the "c-bus" serial clock input. this clock, produced by the controller, is used for transfer timing of commands and data to and from the device. see "c-bus" timing diagram. 4 command data i/p the "c-bus" serial data input from the controller. data is loaded into this device in 8 -bit bytes, msb (b7) first, and lsb (b0) last, synchronised to the serial clock. see "c-bus" timing diagram. 5 reply data o/p the "c-bus" serial data output to the controller. the transmission of reply data bytes is synchronised to the serial clock under the control of the csn input. this 3-state output is held at high impedance when not sending data to the controller. see "c-bus" timing diagram. 6 csn i/p the "c-bus" data loading control function: this input is provided by the controller. data transfer sequences are initiated, completed or aborted by the csn signal. see "c-bus" timing diagram. 7 irqn o/p this output indicates an interrupt condition to the controller by going to a logic "0". this is a "wire- orable" output, enabling the connection of up to 8 peripherals to 1 interrupt port on the controller. this pin has a low impedance pulldown to logic "0" when active and a high- impedance when inactive. an external pullup resistor is required. the conditions that cause interrupts are indicated in the status register and are effective if not masked out by a corresponding bit in the control register. 8 carrier detect o/p the carrier detect output for the ffsk rx.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 5 d/829/4 1.3 signal list (continued) package d2/d5 signal description pin no. name type 9 cardcap o/p the carrier detect integrating capacitor. 10 v bias o/p a bias line for the internal circuitry, held at ? v dd . this pin must be decoupled by a capacitor mounted close to the device pins. 11 mic i/p the ac coupled tx audio input (external amplification is required for use as a microphone input). 12 v ss power the negative supply rail (ground). 13 demodin i/p the ac coupled inverting input to the rx input amplifier (amp1). 14 demodfb o/p the output of the rx input amplifier (amp1) and the input to the audio filter/ limiter section. 15 filter out o/p output of the audio filter/ limiter section. in powersave mode this output is connected to v bias via a 500k w resistor. 16 ffsk/dtmfout o/p the 1200 or 2400 baud ffsk tx output and the dtmf encoder output. when enabled but not transmitting ffsk or dtmf signals, or when in powersave mode, this output is connected to v bias via a 500k w resistor. on power-up, this output can be any level: a general reset command is required to ensure that this output attains v bias initially. 17 sum in i/p input to the audio summing amplifier (amp2). 18 sum out o/p output of the audio summing amplifier (amp2). 19 mod1 in i/p input to mod1 audio gain control. 20 vol in i/p input to the audio volume control. 21 audio out o/p output of the audio volume control. 22 mod1 o/p output of mod1 audio gain control.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 6 d/829/4 1.3 signal list (continued) package d2/d5 signal description pin no. name type 23 mod2 o/p output of mod2 audio gain control. 24 v dd power the positive supply rail. levels and voltages are dependent upon this supply. this pin should be decoupled to v ss by a capacitor. notes: i/p = input o/p = output
baseband signal processor fx829 ? 1997 consumer microcircuits limited 7 d/829/4 1.4 external components c1 22pf 20% r1 1m w 5% x1 4.032mhz 100ppm c2 22pf 20% r2 note 1 10% c3 68pf 20% r3 note 1 10% c4 0.1f 20% r4 100k w 10% c5 0.1f 10% r5 100k w 10% c6 100pf 20% r6 note 2 10% c7 0.1f 20% r7 22k w 10% c8 note 2 20% c9 5.6nf 20% notes : 1. r2, r3, r4 and c3 form the gain components for the summing amplifier (amp2). r2 and r3 should be chosen as required from the system specification, using the following formulae: audio gain = - r 4 r 3 dtmf gain = - r 4 r 2 2. r5, r6, c6 and c8 form the gain components for the rx input amplifier (amp1). r6 should be chosen as required by the signal level, using the following formula: gain = - r 5 r 6 c8 x r6 should be chosen so as not to compromise the low frequency performance of this product. figure 2 recommended external components
baseband signal processor fx829 ? 1997 consumer microcircuits limited 8 d/829/4 1.5 general description the fx829 consists of five main sections: the audio filter section, the programmable attenuators, the dtmf encoder, the ffsk transmitter and the ffsk receiver. all these sections are controlled via a serial ("c-bus") interface. the four sections are described below. audio filtering this consists of an input amplifier and a common audio filter section, which may be switched between rx and tx. the filter section comprises an anti-alias filter followed by low-pass and high-pass filtering with an amplitude limiter to set the maximum deviation. three variable attenuation blocks may be used to set the volume (in rx) or the modulation level (in tx). pre- and de-emphasis can be added externally using resistors and capacitors around amp1, amp2 and the microphone amplifiers, see figure 7. the anti-alias filter is designed to reduce aliasing effects above 50khz which is approximately half the internal filter's sample rate. the filtering is designed to meet the ets 300 086 specification. various powersave modes are incorporated. mod1 and mod2 attenuators the mod1 input can be connected directly to sum out, so that the mod1 and mod2 outputs can then be used for two point modulation. alternatively, the mod1 attenuator can be used for auxiliary gain adjustment, in which case the input signal must be ac coupled with a suitable capacitor. dtmf encoder this generates the standard dtmf tones according to the control 2 register settings. it also has a powersave mode. ffsk tx the tx function of the ffsk modem operates continuously in a free format mode, which means that the preamble and frame sync have to be programmed like normal data bytes. however, a 2-byte checksum may be generated automatically by simply marking the beginning and end of the data to be used. any number of whole bytes may be used to generate the checksum. after the last byte has been transmitted one additional "hang bit" is automatically added to the end. all tx operations are programmed from the "c-bus" via an 8-bit buffer. the tx part of the ffsk modem has a powersave mode. the modulation output is one cycle of 1200hz for a "1" and one and a half cycles of 1800hz for a "0" at 1200 baud, or one half cycle of 1200hz for a "1" and one cycle of 2400hz for a "0" at 2400 baud. ffsk rx in rx, the modem automatically achieves bit sync and then recognises the previously selected sync and/or synt word of the mpt1327, ets 300 230 or paa1382 specifications. at the same time as the above, it can also recognise a user programmed 16-bit rx sync word. on reception of the sync, synt or rx sync word, the device will automatically (or manually at any time) start checking the data and checksum. it provides a 1-bit correct/incorrect result every byte, so that any number of bytes can be checked. the rx part of the ffsk modem operates at 1200 or 2400 baud and has a powersave mode. both ffsk rx and tx work in half duplex mode.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 9 d/829/4 1.5.1 software description address/commands instructions and data are transferred, via "c-bus", in accordance with the timing information given in figure 11. instruction and data transactions to and from the fx829 consist of an address/command (a/c) byte followed by either: ( i) a further instruction or data (1 or 2 bytes) or (ii) a status or rx data reply (1 byte) 8-bit write only registers hex address/ command register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) $01 reset n/a n/a n/a n/a n/a n/a n/a n/a $10 control 1 amp1 amp2 audio ffskrx ffsktx uk/f mic b/w $11 control 2 chksum dtmfen dtmfhi dtmflo dtmf3 dtmf2 dtmf1 dtmf0 $13 audio <-------------------------- gain --------------------------> attenuation 0 0 0 bit 4 bit 3 bit 2 bit 1 bit 0 $40 control 3/ irq enable 0 1200/2400 txidlem rxdatam txdatam rx sync word prime synt prime sync prime $43 txdata <----------------------------------------------- txdata -----------------------------------------------> bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16-bit write only registers hex address/ command register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) $12 mod levels mod 1 <-------------------------- mod 1 --------------------------> (1) 0 0 enable bit 4 bit 3 bit 2 bit 1 bit 0 <-------------------------- mod 2 --------------------------> (2) 0 0 0 bit 4 bit 3 bit 2 bit 1 bit 0 $44 rx sync <------------------------------------------- rx sync word -----------------------------------------> word (1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 <------------------------------------------- rx sync word -----------------------------------------> (2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write only register description reset register (hex address $01) the reset command has no data attached to it. it sets the device registers into the specific states as listed below:
baseband signal processor fx829 ? 1997 consumer microcircuits limited 10 d/829/4 register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 d0) control 1 0 0 0 0 0 0 0 0 control 2 0 0 0 0 0 0 0 0 control 3/irq enable 0 0 0 0 0 0 0 0 audio attenuation 0 0 0 0 0 0 0 0 txdata x x x x x x x x mod levels (1) 0 0 0 0 0 0 0 0 mod levels (2) 0 0 0 0 0 0 0 0 rx sync word (1) x x x x x x x x rx sync word (2) x x x x x x x x status 0 0 0 0 0 0 0 0 rxdata x x x x x x x x x = undefined control1 register (hex address $10) this register is used to control the functions of the device as described below: amp1 (bit 7) when this bit is "1", amp1 is enabled. when this bit is "0", amp1 is disabled (i.e. powersaved). amp2 (bit 6) when this bit is "1", both amp2 and mod2 are enabled. when this bit is "0", both amp2 and mod2 are disabled (i.e. powersaved) and the mod2 output is pulled to v bias via a 1m w resistor. audio (bit 5) when this bit is "1", the audio filter/ limiter section is enabled. when this bit is "0", the audio filter/ limiter section is disabled (i.e. powersaved). ffskrx (bit 4) when this bit is "1", the ffsk rx is enabled. when this bit is "0", the ffsk rx is disabled (i.e. powersaved). note: 1. the ffsk rx and tx cannot both be enabled at the same time. if both ffskrx and ffsktx are "1", then they will both be disabled (i.e. powersaved). ffsktx (bit 3) when this bit is "1", the ffsk tx is enabled. when this bit is "0", the ffsk tx is disabled (i.e. powersaved). note: 1. the ffsk tx and rx cannot both be enabled at the same time. if both ffsktx and ffskrx are "1", then they will both be disabled (i.e. powersaved). 2. the dtmf encoder and ffsk tx cannot both be enabled at the same time. if both dtmfen and ffsktx are "1", the n they will both be disabled. uk/f (bit 2) when this bit is "1", the sync/synt is set to the paa standard of "1011010000110011" (sync) when this bit is "0", the sync/synt is set to the mpt standard of "1100010011010111" (sync)
baseband signal processor fx829 ? 1997 consumer microcircuits limited 11 d/829/4 mic (bit 1) when this bit is "1", the mic input is enabled and the amp1 (demodin) input is disabled. when this bit is "0", the amp1 (demodin) input is enabled and the mic input is disabled. b/w (bit 0) when this bit is "1", the bandwidth of the audio path is set wide for 20khz/25khz rf channel spacing. when this bit is "0", the bandwidth of the audio path is set narrow for 12.5khz rf channel spacing. control 2 register (hex address $11) this register is used to control the functions of the device as described below: chksum (bit 7) in the tx mode, when this bit is "1", the checksum generator is enabled. all complete bytes that are transmitted after this time are used in the checksum calculation. when this bit goes from "1" to "0", the checksum generator will complete its calculations on the current byte and the result will be sent as the next two bytes of transmitted data. in the rx mode, the "0" to "1" transition of the chksum bit is used at the start of the next byte received at demodin to manually reset the rx checksum calculation, see figure 4. the calculation can also be reset automatically by a sync, synt, or rx sync word detection - see control 3 / irq enable register. in this case, the rx checksum calculation starts with the first data byte after the 2-byte sync word has been detected. the chksum bit can be reset to "0" at any time. the result of the checksum is made available in the status register after the reception of every complete byte (see rxsumf bit of the status register). note that the device is designed to work with any message length, and as a consequence it is not aware of the position of the checksum within the incoming data message. it thus performs a checksum assessment after every received byte. the controlling software should use its knowledge of the system message length in order to determine which rxsumf reading is valid, i.e. after the second of the two checksum bytes has been received. the timing of data bytes relative to the checksum bit is shown in figures 3 and 4.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 12 d/829/4 figure 3 checksum generation in tx mode figure 4 checksum calculation in rx mode
baseband signal processor fx829 ? 1997 consumer microcircuits limited 13 d/829/4 dtmfen (bit 6) when this bit is "1", the dtmf output is enabled. when this bit is "0", the dtmf output is disabled. as the powersave of the dtmf is performed in the dtmfhi and dtmflo registers, this bit allows a fast start up time for the tones. note: 1. the dtmf encoder and ffsk tx cannot both be enabled at the same time. if both dtmfen and ffsktx are "1", then they will both be disabled. dtmfhi (bit 5) when this bit is "1", the dtmf high frequency tone generator is enabled. it will not appear on the output pin unless or until the dtmfen is "1". when this bit is "0", the dtmf high frequency tone generator is disabled (i.e. powersaved). dtmflo (bit 4) when this bit is "1", the dtmf low frequency tone generator is enabled. it will not appear on the output pin unless or until the dtmfen is "1". when this bit is "0", the dtmf low frequency tone generator is disabled (i.e. powersaved). dtmf3, dtmf2, dtmf1, dtmf0 (bit 3, bit 2, bit 1, bit 0) these four bits define the dtmf tones according to the table below: bit 3 bit 2 bit 1 bit 0 dtmf tones dtmf 'digit' 0 0 0 0 1209hz + 697hz 1 0 0 0 1 1209hz + 770hz 4 0 0 1 0 1209hz + 852hz 7 0 0 1 1 1209hz + 941hz * 0 1 0 0 1337hz + 697hz 2 0 1 0 1 1337hz + 770hz 5 0 1 1 0 1337hz + 852hz 8 0 1 1 1 1337hz + 941hz 0 1 0 0 0 1478hz + 697hz 3 1 0 0 1 1478hz + 770hz 6 1 0 1 0 1478hz + 852hz 9 1 0 1 1 1478hz + 941hz # 1 1 0 0 1634hz + 697hz a 1 1 0 1 1634hz + 770hz b 1 1 1 0 1634hz + 852hz c 1 1 1 1 1634hz + 941hz d
baseband signal processor fx829 ? 1997 consumer microcircuits limited 14 d/829/4 audio attenuation register (hex address $13) the five least significant bits in this register are used to set the attenuation of the audio volume control according to the table below: 4 3 2 1 0 audio attenuation 0 0 0 0 0 off 0 0 0 0 1 48.0db 0 0 0 1 0 46.4db 0 0 0 1 1 44.8db 0 0 1 0 0 43.2db 0 0 1 0 1 41.6db 0 0 1 1 0 40.0db 0 0 1 1 1 38.4db 0 1 0 0 0 36.8db 0 1 0 0 1 35.2db 0 1 0 1 0 33.6db 0 1 0 1 1 32.0db 0 1 1 0 0 30.4db 0 1 1 0 1 28.8db 0 1 1 1 0 27.2db 0 1 1 1 1 25.6db 1 0 0 0 0 24.0db 1 0 0 0 1 22.4db 1 0 0 1 0 20.8db 1 0 0 1 1 19.2db 1 0 1 0 0 17.6db 1 0 1 0 1 16.0db 1 0 1 1 0 14.4db 1 0 1 1 1 12.8db 1 1 0 0 0 11.2db 1 1 0 0 1 9.6db 1 1 0 1 0 8.0db 1 1 0 1 1 6.4db 1 1 1 0 0 4.8db 1 1 1 0 1 3.2db 1 1 1 1 0 1.6db 1 1 1 1 1 0db bits 5, 6 and 7 should always be set to "0". control 3 / irq enable register (hex address $40 ) this register is a mixture of control bits and interrupt mask bits, as detailed below: bit 7 not used, set to zero. 1200/2400 (bit 6) when this bit is "1", the ffsk rx and tx are set to operate at 1200 baud. when this bit it "0", the ffsk rx and tx are set to operate at 2400 baud.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 15 d/829/4 txidlem (bit 5) when this bit is "1", the txidle interrupt will be gated out to the irqn pin. when this bit is "0", the txidle interrupt will be inhibited. this bit has no effect on the contents of the status register. rxdatam (bit 4) when this bit is "1", the rxdata interrupt will be gated out to the irqn pin. when this bit is "0", the rxdata interrupt will be inhibited. this bit has no effect on the contents of the status register. txdatam (bit 3) when this bit is "1", the txdata interrupt will be gated out to the irqn pin. when this bit is "0", the txdata interrupt will be inhibited. this bit has no effect on the contents of the status register. rx sync word prime (bit 2) when this bit is set to "1", it enables the rx sync word detection. it is cleared/disabled when a sync, synt, or rx sync word is detected. it may also be cleared/disabled by writing "0" directly to this bit. synt prime (bit 1) when this bit is set to "1", it enables the synt detection. it is cleared/disabled when a sync, synt, or rx sync word is detected. it may also be cleared/disabled by writing "0" directly to this bit. sync prime (bit 0) when this bit is set to "1", it enables the sync detection. it is cleared/disabled when a sync, synt, or rx sync word is detected. it may also be cleared/disabled by writing "0" directly to this bit. txdata register (hex address $43) this is the tx data output register. it is double buffered, thus giving the user up to 8 bit periods to load in the next 8 bits. ffsk data is transmitted immediately it is loaded if the transmitter is idle. data is transmitted in 8- bit bytes, bit 7 (msb) will be transmitted first.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 16 d/829/4 mod levels register (hex address $12) the six least significant bits of the first byte in this register are used to set the attenuation of the modulator 1 amplifier and the five least significant bits of the second byte in this register are used to set the attenuation of the modulator 2 amplifier, according to the tables below: 5 4 3 2 1 0 mod. 1 attenuation 4 3 2 1 0 mod. 2 attenuation 0 x x x x x disabled (v bias ) 1 0 0 0 0 0 >40db 0 0 0 0 0 >40db 1 0 0 0 0 1 12.0db 0 0 0 0 1 6.0db 1 0 0 0 1 0 11.6db 0 0 0 1 0 5.8db 1 0 0 0 1 1 11.2db 0 0 0 1 1 5.6db 1 0 0 1 0 0 10.8db 0 0 1 0 0 5.4db 1 0 0 1 0 1 10.4db 0 0 1 0 1 5.2db 1 0 0 1 1 0 10.0db 0 0 1 1 0 5.0db 1 0 0 1 1 1 9.6db 0 0 1 1 1 4.8db 1 0 1 0 0 0 9.2db 0 1 0 0 0 4.6db 1 0 1 0 0 1 8.8db 0 1 0 0 1 4.4db 1 0 1 0 1 0 8.4db 0 1 0 1 0 4.2db 1 0 1 0 1 1 8.0db 0 1 0 1 1 4.0db 1 0 1 1 0 0 7.6db 0 1 1 0 0 3.8db 1 0 1 1 0 1 7.2db 0 1 1 0 1 3.6db 1 0 1 1 1 0 6.8db 0 1 1 1 0 3.4db 1 0 1 1 1 1 6.4db 0 1 1 1 1 3.2db 1 1 0 0 0 0 6.0db 1 0 0 0 0 3.0db 1 1 0 0 0 1 5.6db 1 0 0 0 1 2.8db 1 1 0 0 1 0 5.2db 1 0 0 1 0 2.6db 1 1 0 0 1 1 4.8db 1 0 0 1 1 2.4db 1 1 0 1 0 0 4.4db 1 0 1 0 0 2.2db 1 1 0 1 0 1 4.0db 1 0 1 0 1 2.0db 1 1 0 1 1 0 3.6db 1 0 1 1 0 1.8db 1 1 0 1 1 1 3.2db 1 0 1 1 1 1.6db 1 1 1 0 0 0 2.8db 1 1 0 0 0 1.4db 1 1 1 0 0 1 2.4db 1 1 0 0 1 1.2db 1 1 1 0 1 0 2.0db 1 1 0 1 0 1.0db 1 1 1 0 1 1 1.6db 1 1 0 1 1 0.8db 1 1 1 1 0 0 1.2db 1 1 1 0 0 0.6db 1 1 1 1 0 1 0.8db 1 1 1 0 1 0.4db 1 1 1 1 1 0 0.4db 1 1 1 1 0 0.2db 1 1 1 1 1 1 0db 1 1 1 1 1 0db x = don't care mod1 enable (bit 5, first byte) when this bit is "1" the mod1 attenuator is enabled. when this bit is "0" the mod1 attenuator is disabled (i.e. powersaved). bits 6 and 7 in the first byte and bits 5, 6 and 7 in the second byte should always be set to "0". mod levels (1) register is loaded first. note: the mod2 attenuator is enabled by the amp2 enable signal (bit 6 of control1 register). rx sync word register (hex $44) this is a two byte register that defines the 16-bit programmable synchronisation word. this word is compared with the incoming rx data and, if a match is found, it is indicated in the status register and an interrupt is generated. bit 15, the msb of the first byte, is loaded first.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 17 d/829/4 8-bit read only registers hex address/ command register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) $41 status 0 rxsumf txidlef rxdataf txdataf rx sync wordf syntf syncf $42 rxdata <--------------------------------------------- rxdata ---------------------------------------------> bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read only register description status register (hex address $41 ) this register is used to indicate the status of the device as described below: bit 7 not used, always set to zero. rxsumf (bit 6) when this bit is "1", the rx checksum is correct. when this bit is "0", the rx checksum is incorrect. this bit is updated and latched in after reception of every eight bits (see chksum bit of the control2 register). txidlef (bit 5) when all the tx data and any checksum and one "hang-bit" have been transmitted, this bit will be set to "1" to indicate that the transmitter is idle. this bit is reset to "0" immediately after reading the status register. when this bit is set to "1", an interrupt may be generated depending on the state of the txidlem bit in the control 3 / irq enable register. rxdataf (bit 4) when a full byte of data is received and is available in the rxdata register, this bit will be set to "1". this bit is reset to "0" immediately after reading the status register. when this bit is set to "1" an interrupt may be generated depending on the state of the rxdatam bit in the control 3 / irq enable register. txdataf (bit 3) when the tx data buffer is empty this bit will be set to "1". this bit is reset to "0" immediately after reading the status register. when this bit is set to "1", an interrupt may be generated depending on the state of the txdatam bit in the control 3 / irq enable register. rx sync wordf (bit 2) this bit is only defined when rx sync word prime is enabled. when the data sequence specified in the rx sync word register has been successfully matched to the rx incoming data, this bit will be set to "1". this bit is reset to "0" immediately after reading the status register. when this bit is set to "1", an interrupt will be generated, the checksum generator and byte counter will be reset and sync prime, synt prime and rx sync word prime will be reset. syntf (bit 1) this bit is only defined when synt prime is enabled. when the data sequence specified by synt has been successfully matched to the rx incoming data, this bit will be set to "1". this bit is reset to "0" immediately after reading the status register. when this bit is set to "1", an interrupt will be generated, the checksum generator and byte counter will be reset and sync prime, synt prime and rx sync word prime will be reset.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 18 d/829/4 syncf (bit 0) this bit is only defined when sync prime is enabled. when the data sequence specified by sync has been successfully matched to the rx incoming data, this bit will be set to "1". this bit is reset to "0" immediately after reading the status register. when this bit is set to "1", an interrupt will be generated, the checksum generator and byte counter will be reset and sync prime, synt prime and rx sync word prime will be reset. rxdata register (hex address $42) this register contains the last byte of data received. it is updated every 8 bits at the same time as the rxsumf bit in the status register is updated. the rxdata register is double buffered, thus giving the user up to 8 bit periods to read the data before it is overwritten by the next byte. 1.5.2 ffsk checksum generation and checking generation the checksum generator takes the m x 8 bits from the m bytes of information, sequentially loaded into the txdata register and divides them modulo-2, by the generating polynomial: x 15 + x 14 + x 13 + x 11 + x 4 + x 2 + 1 it then takes the 15-bit remainder from the polynomial divider, inverts the last bit and appends an even parity bit generated from the initial m x 8 bits and the 15-bit remainder (with the last bit inverted). this 16-bit word is used as the "checksum". see figure 5. (m = the number of bytes in the information to be sent) figure 5 checksum generation
baseband signal processor fx829 ? 1997 consumer microcircuits limited 19 d/829/4 checking the checksum checker performs two tasks: it takes the first n-1 bits of a received (n = 8m + 16 bits) message, inverts bit n-1, and divides them modulo-2, by the generating polynomial: x 15 + x 14 + x 13 + x 11 + x 4 + x 2 + 1 the 15 bits remaining in the polynomial divider are checked for all zero. secondly, it generates an even parity bit from the first n-1 bits of a received message and compares this bit with the received parity bit (bit n). see figure 6. if the 15 bits in the polynomial divider are all zero, and the two parity bits are equal, then the rxsumf bit (status register bit 6) is set. this is updated and latched every 8 bits, starting at the bit immediately after the initialisation of the bit counter. this initialisation takes place on detection of frame synchronisation, i.e. the matching of received data to the sync, synt or rx sync word. note that the checksum is calculated on the received data before it is double buffered (see figure 4). n = the number of bits in the received message m = the number of bytes of transmitted data, excluding checksum figure 6 checksum checking
baseband signal processor fx829 ? 1997 consumer microcircuits limited 20 d/829/4 1.6 application notes the following block diagrams show the possible arrangements for the pre- and de-emphasis required by paa1382 and mpt1327 specifications. figure 7a transmitter pre-emphasis (showing both pre-emphasis positions, as required by the paa1382 specification. remove pre-emphasis 2 for the mpt1327 specification requirement) figure 7b paa1382 receiver de-emphasis (showing position of de-emphasis in all paths, as required by the paa1382 specification) figure 7c mpt1327 receiver de-emphasis (showing position of de-emphasis in audio path only, as required by the mpt1327 specification)
baseband signal processor fx829 ? 1997 consumer microcircuits limited 21 d/829/4 the fx829 should be programmed in the following manner: 1. perform a general reset when first applying power to the fx829. 2. program the fx829 configuration whilst in powersave. e.g. uk/f, mic, b/w, 1200/2400, dtmf0-3, dtmfhi, dtmflo, txidlem, rxdatam, txdatam, rx sync word prime, synt prime, sync prime, mod1, mod2, rx sync word and audio attenuator. 3. take the appropriate parts of the fx829 out of powersave by enabling: amp1, amp2, mod1, mod2, audio and (dtmfen or ffsktx or ffskrx). 4. in dtmf tx mode, a dtmf tone will be generated for the duration that dtmfen is set to ? 1 ? . 5. in ffsk rx mode, wait for an interrupt (irqn = ? 0 ? ) or poll the status register. remember that all status flags are reset after reading the status register. (a) if rxsyncwordf, syntf or syncf become set to ? 1 ? , the corresponding synchronisation word has been detected. this indicates the start of valid rx data. the checksum calculation will be automatically reset. note that the timing of rxdataf will be re-aligned by the generation of a sync, synt or rx sync word interrupt. (b) when rxdataf subsequently becomes set to ? 1 ? , read the rx data from the rxdata register. (note that rxdataf will be set every 8 bits regardless of whether valid rx data is being received or not. sync and checksum patterns should be considered for validating the data). (c) if rxsumf becomes set to ? 1 ? , then all of the rx data sent (starting after the synchronisation word and terminating with a checksum) will have been correctly received. note that it is necessary to know in advance what message length is expected, in order to determine at which point rxsumf is valid (i.e. after the interrupt for the second checksum data byte being received has occurred). the rxsumf bit is invalid at all other times. when rxsumf becomes set to ? 1 ? , the last two bytes of rx data received will represent the two- byte checksum transmitted. the first checksum byte will already have been read from the rxdata register, the last byte is available to be read, as the rxdataf bit will also have been set to ? 1 ? . 6. in ffsk tx mode, wait for an interrupt (irqn = ? 0 ? ) or poll the status register. remember that all status flags are reset after reading the status register. (a) do not send tx data until the txdataf bit has been set to ? 1 ? . when the txdataf bit is next set to ? 1 ? , write the first byte of tx data to the txdata register. if the transmit buffer is empty, this data will be transmitted immediately, causing the txdataf bit to be set to ? 1 ? approximately one ffsk bit-period after the txdata register has been loaded with data. (any txidlef bit set upon entering ffsk tx mode should be ignored). (b) the next byte of tx data should be written to the txdata register as soon as the txdataf bit has been set to ? 1 ? . once this has been done, the txdataf bit will again be set to ? 1 ? eight ffsk bit-periods after the txdata register was loaded with the second byte of data.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 22 d/829/4 (c) subsequent bytes of tx data should be written to the txdata register as soon as the txdataf bit has been set to ? 1 ? . after the last byte of tx data has been loaded, the txdataf bit will be set after both 8 and 16 ffsk bit-periods followed by the txidlef bit which will be set approximately one ffsk bit-period later, to indicate that the final bit has been transmitted. (d) the txdataf bit will continue to be set every 8 ffsk bit-periods, regardless of whether tx data is written to the txdata register or not, providing the transmitter is enabled (ffsk tx mode = ffsktx bit set to ? 1 ? ). note that whilst the 2-byte checksum is being generated and transmitted, the txdataf bit will not be set for approximately 24 ffsk bit-periods.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 23 d/829/4 figure 8 reception of 2 bytes of data
baseband signal processor fx829 ? 1997 consumer microcircuits limited 24 d/829/4 figure 9 transmission of 3 bytes of data
baseband signal processor fx829 ? 1997 consumer microcircuits limited 25 d/829/4 1.7 performance specification 1.7.1 electrical performance absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd - v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current into or out of v dd and v ss pins -30 +30 ma current into or out of any other pin -20 +20 ma d2 package min. max. units total allowable power dissipation at tamb = 25c 800 mw ... derating 13 mw/c storage temperature -40 +85 c operating temperature -40 +85 c d5 package min. max. units total allowable power dissipation at tamb = 25c 550 mw ... derating 9 mw/c storage temperature -40 +85 c operating temperature -40 +85 c operating limits correct operation of the device outside these limits is not implied. notes min. max. units supply (v dd - v ss ) 3.0 5.5 v operating temperature -40 +85 c xtal frequency 4.0315968 4.0324032 mhz
baseband signal processor fx829 ? 1997 consumer microcircuits limited 26 d/829/4 operating characteristics for the following conditions unless otherwise specified: xtal frequency = 4.032mhz, bit rate = 1.2k bits/sec, noise bandwidth = bit rate, audio level 0db ref = 308mvrms at 1khz v dd = 3.3v to 5.0v, tamb = -40c to +85c. notes min. typ. max. units dc parameters i dd ( powersaved) (v dd = 5.0v) 2 - 0.6 1.5 ma i dd ( tx or rx voice) (v dd = 5.0v) 2 - 5.0 8.0 ma i dd ( powersaved) (v dd = 3.3v) 2 - 0.3 1.0 ma i dd ( tx or rx voice) (v dd = 3.3v) 2 - 2.7 4.0 ma "c-bus" interface input logic "1" 70% - - v dd input logic "0" - - 30% v dd input leakage current (logic "1" or "0") -1.0 - 1.0 a input capacitance - - 7.5 pf output logic "1" (i oh = 120a) 90% v dd output logic "0" (i ol = 360a) 10% v dd "off" state leakage current ( vout = v dd ) 9 - - 10 a a c parameters input sensitivity (for 0db output) tx audio input (mic) 8 - 308 - mvrms rx audio input (demodfb) 8 - 308 - mvrms output drive level for 60% deviation 1, 6, 8 291 308 326 mvrms for 100% deviation 1, 6, 7, 8 - 1440 - mvpk-pk audio filters gain at 1khz 5 - 0 - db passband ripple 5 -2.0 - 0.5 db sinad 5, 14 - 59 - dbp signal path noise 5 - -55 - db narrrow audio bandwidth setting passband frequencies 5 300 - 2550 hz stopband attenuation: (f = 100hz) 5 - 3.0 - db (f = 3400hz) 5 - 5.5 - db (f = 6000hz) 5 10.5 24 - db (f = 12500hz) 5 25 49 - db wide audio bandwidth setting passband frequencies 5 300 - 3000 hz stopband attenuation: (f = 100hz) 5 - 3.0 - db (f = 3400hz) 5 - 3.0 - db (f = 6000hz) 5 10.5 19 - db (f = 25000hz) 5 39.5 68 - db
baseband signal processor fx829 ? 1997 consumer microcircuits limited 27 d/829/4 notes min. typ. max. units amp 1 and amp 2 open loop gain (i/p = 1mv at 100hz) - 70 - db unity gain bandwidth - 5.0 - mhz input impedance (at 100hz) 10 - - m w output impedance (open loop) - 6.0 - k w (closed loop) - 600 - w distortion (dtmf) - 2 5 % ffsk/dtmf tx out tx o/p impedance (not powersaved) 3 1.0 2.5 k w tx o/p impedance ( powersaved) 3 300 500 - k w signal level (ffsk) 1 -1 0 +1 db signal level (dtmf high tone) 1 - +2.0 - db signal level (dtmf low tone) 1 - 0 - db distortion (dtmf) - 2 5 % ffsk tx out isochronous distortion: (1200hz - 1800hz) 25 40 s (1800hz - 1200hz) 25 40 s (1200hz - 2400hz) 20 30 s (2400hz - 1200hz) 20 30 s third harmonic distortion 2 3 % deviation limiter threshold 1 - 1300 - mvpk-pk gain -0.5 - 0.5 db transmitter modulator drives input impedance (mod1 in, volume in) (at 100hz) - 15.0 - k w mod.1 attenuator nominal adjustment range 0 12.0 db attenuation accuracy -1.0 - 1.0 db step size 0.2 0.4 0.6 d b output impedance 3 - 600 - w mod.2 attenuator nominal adjustment range 0 6.0 db attenuation accuracy -0.6 - 0.6 db step size 0.1 0.2 0.3 db output impedance 3 - 600 - w audio output attenuator nominal adjustment range 0 48.0 db attenuation accuracy -1.5 - 1.5 db step size - 1.6 - db output impedance 3 - 600 - w
baseband signal processor fx829 ? 1997 consumer microcircuits limited 28 d/829/4 notes min. typ. max. units ffsk receiver signal input dynamic range (snr = 50db) 10, 11 100 230 1000 mvrms bit error rate (snr = 12db at 1200 baud) 11 - 2.5 - 10 - 4 (snr = 12db at 2400 baud) 11 - 1.5 - 10 - 3 (snr = 20db at 1200/2400 baud) 11 - 1.0 - 10 - 8 receiver synchronisation (snr = 12db) 12 probability of bit 16 being correct 0.995 carrier detect sensitivity 12, 13 - - 150 mvrms probability of carrier detection - after bit 16 (snr = 12db) 0.995 - with 230mvrms noise (no signal) 0.05 miscellaneous impedances filter out - 600 - w tx audio input (mic) (at 100hz) 10 - - m w xtal/clock input 'high' pulse width 4 40 ns 'low' pulse width 4 40 ns input impedance (at 100hz) 10 m w gain (i/p = 1mvrms at 100hz) 20 db notes: 1. at v dd = 5.0v only. signal levels are proportional to v dd . 2. not including any current drawn from the modem pins by external circuitry. powersaved = all functions disabled. tx or rx = device configured into any half-duplex operating mode. currents measured at tamb = 25c only. 3. small signal impedance, at v dd = 5.0v and tamb = 25c. a minimum load resistance of 6k w is suggested. 4. timing for an external input to the xtal/clock pin. 5. between mic or amp1 inputs to modulator and audio outputs, see figures 10a and 10b. 6. it is recommended that these output levels are used to produce 60% or 100% deviation in the transmitter. 7. with the tx audio input level 20db above the level required to produce 0db at the output drives. 8. with output gains set to 0db. 9. irqn pin. 10. see figure 13 (variation of ber with input signal level). 11. snr = signal to noise ratio in the bit rate bandwidth. 12. for a "10101010101 ...01" pattern. 13. measured with a 150mvrms input signal (no noise). 14. dbp represents a psophometrically weighted measurement.
baseband signal processor fx829 ? 1998 consumer microcircuits limited 29 d/829/4 frequency (hz) gain (db) -60 -50 -40 -30 -20 -10 0 10 10 100 1,000 10,000 100,000 2. 55k 0. 5db - 2db - 10. 5 db - 14 db/ oct ave response must not exceed th i s l i mi t 6k 20k 300 figure 10a overall audio frequency response for 12.5khz channel separation frequency (hz) gain (db) -60 -50 -40 -30 -20 -10 0 10 10 100 1,000 10,000 100,000 0. 5db - 2db - 10. 5 db - 14 db/ oct ave response must not exceed th i s l i mi t 6k 20k 300 3k figure 10b overall audio frequency response for 20khz/25khz channel separation
baseband signal processor fx829 ? 1997 consumer microcircuits limited 30 d/829/4 1.7.1 electrical performance (continued) figure 11 "c-bus" timing for the following conditions unless otherwise specified: xtal frequency = 4.032mhz, v dd = 3.3v to 5.0v, tamb = -40c to +85c. parameter notes min. typ. max. units t cse "cs-enable to clock-high" 2.0 - s t csh last "clock-high to cs-high" 4.0 - s t hiz "cs-high to reply output 3-state" - 2.0 s t csoff "cs-high" time between transactions 2.0 - s t nxt "inter-byte" time 4.0 - s t ck "clock-cycle" time 2.0 - s notes: 1. depending on the command, 1 or 2 bytes of command data are transmitted to the peripheral msb (bit 7) first, lsb (bit 0) last. reply data is read from the peripheral msb (bit 7) first, lsb (bit 0) last. 2. data is clocked into and out of the peripheral on the rising serial clock edge. 3. loaded commands are acted upon at the end of each command. 4. to allow for differing controller serial interface formats "c-bus" compatible ics are able to work with either polarity serial clock pulses.
baseband signal processor fx829 ? 1997 consumer microcircuits limited 31 d/829/4 figure 12 bit error rate graph figure 13 typical variation of bit error rate with input signal level
baseband signal processor fx829 ? 1997 consumer microcircuits limited 32 d/829/4 1.7.2 packaging figure 14 d2 mechanical outline: order as part no. fx829d2 figure 15 d5 mechanical outline: order as part no. fx829d5
baseband signal processor fx829 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed. consumer microcircuits limited 1 wheaton road telephone: +44 1376 513833 witham - essex telefax: +44 1376 518247 cm8 3td - england e-mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk figure 16 p4 mechanical outline: order as part no. FX829P4

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